The present invention relates to a wiring layer of an aluminum alloy for high density integrated circuits.
FIG. 8 is a fragmentary plan view of a conventional semiconductor device according to "Electronic Integrated Circuits, J. Allison, McGraw-Hill, 1975, Chapter 1". FIG. 9 is a sectional view taken along the line A--A shown in FIG. 8. In these figures, the semiconductor device has a semiconductor substrate 1, circuit elements (none of which are shown), such as transistors, capacitors and resistors, which are formed on the substrate 1, an insulating film 2 formed over these circuit elements in such a manner as to cover them, and wiring portions 3 to 5 of an aluminum alloy which are formed on the insulating film 2. The wiring portion 3 acts as a power line or ground line, while the wiring portions 4 and 5 act as lines enabling connections for other purposes.
The semiconductor device constructed as described above is manufactured in the following manner. Circuit elements, such as transistors, capacitors and resistors (not shown), which are required for the circuit construction are first formed on the substrate 1. Thereafter, the insulating film 2 which provides the foundation for the wiring is formed over these elements. Subsequently, contact holes (none of which are shown) are formed in the insulating film 2 at locations thereof corresponding to those of terminals and electrodes of the elements which are to be connected to a wiring layer that will be formed in the following process. The wiring layer, which is formed of an aluminum alloy, is then formed on the entire upper surface of the insulating film 2 to a thickness of 0.5 to 1.5 .mu.m. Finally, this wiring layer is patterned into a predetermined planar configuration by a photolithography method, thereby obtaining the wiring portions 3 to 5 shown in FIGS. 8 and 9.
With such a semiconductor device, the width of each wiring portion and the space between two adjacent ones are very important factors which determine the integration density of the circuit concerned, these wiring portions being formed of an aluminum alloy. Accordingly, various attempts have been made to reduce the width of the wiring portions and also the space between two adjacent wiring portions, so as to improve the integration density of the circuit concerned. As a result, it has become possible to form a wiring pattern wherein the width of a wiring portion and the space between two adjacent wiring portions may each be 2 .mu.m or less.
It should be noted that, with respect to a wiring portion which is used as a power line or ground line and through which current of a large magnitude flows, it is necessary for the wiring portion to have a width of at least about 5 .mu.m. This is to avoid the physical phenomenon known as "electro-migration" in which, when current of a high density flows through a wiring portion, atoms of the metal forming the wiring move. In general, it is known that, in aluminum wiring, when the current density exceeds 1.times.10.sup.5 A/cm.sup.2, such a phenomenon will occur. For this reason, the wiring portion 3 which acts as a power line or ground line is made wider than the other wiring portions 4 or 5, as shown in FIGS. 8 and 9.
However, when wiring portion 3 is formed of an aluminum alloy, hillocks or projections 3a, as shown in FIGS. 8 and 9, may be formed at edges of the wiring portion 3. Projections 3a may be formed when the semiconductor device is subjected to a heat treatment such as annealing. The metal material forming the wiring portion 3 may be softened and partially displaced during the heat treatment. It has been confirmed in certain experiments conducted by the present inventors that these hillocks 3a are often formed on the edges of a wide wiring portion which has, as the wiring portion 3 does, a width of 5 .mu.m or more. Hillocks are rarely formed on a narrow wiring portion having, as the wiring portions 4 and 5 do, a width of 2 .mu.m or less. It has also been confirmed that a hillock may sometimes have a length (i.e., a horizontal dimension as viewed in FIG. 9) of 2 .mu.m or more. As a result, as shown in FIGS. 8 and 9, some of the hillocks 3a may become long enough to cross the space between the wiring portion 3 and the adjacent wiring portion 4, causing short-circuiting between wiring portions 3 and 4.
With a conventional integrated circuit semiconductor device, it is necessary to provide a space of 2 .mu.m or more between edge portions of a wide wiring portion which acts as a power line or ground line and an adjacent wiring portion in order to prevent the occurrence of short-circuiting. It has therefore been difficult to achieve high density wiring layers in integrated circuits and, hence, to achieve a high integration density.